Phase locking control device



March 30, 1965 Filed July 2, 1962 T. H. GIFFT PHASE LOCKING CONTROL DEVICE 4 Sheets-Sheet l 7 l2 I4 I I PULSE J1- SHIFT 2 SPEED UP SIGNAL S'GNAL REGISTER SOURCE IL 3 s| ow DOWN SIGNAL |6 5 V CONTROLLED DEVICE gg gg FIG. l

I9 I/ l? PULSE IL SHIFT LEFT l S'GNAL PULSE PULSES i i GlsTER 2 SOURCE JL. RESOLVER SHIFT RIGHT T PULSES I I8 I4 I I I I ROTATION CONTROL LIST I; SENSOR MQTOR DEVICE SOHRCE FIG. 2

INVENTOR THOMAS H. GIFFT BY iwajm ATTORNEY 503' I I M iii?" T March 30, 1965 T. H. GIFFT 3,176,208

PHASE LOCKING CONTROL DEVICE Filed July 2, 1962 4 Sheebs$hee 2 H 1r r39 TO SHIFT REGISTER II 7| M T0 SHIFT REGISTER 43 k V J n FIG 3 INVENTOR. THOMAS H. GIFFT QJM ATTORNEY March 30, 1965 "r. H. GIFFT PHASE LOCKING CONTROL DEVICE 4 Sheets-Sheet 3 Filed July 2, 1962 FIG INVENTOR. THOMAS H GIFFT BY 2 9 ATTORNEY March 30, 1965 Filed July 2, 1962 T. H. GIFFT 3,176,208

PHASE LOCKING CONTROL DEVICE 4 Sheets-Sheet 4 E; El: fi 3 INVENTOR. THOMAS H. GIFFT ATTORNEY United States Patent 3,176,2ll8 PHASE LOiIKlNG QONTRQL DEVHQEE Thomas H. Gilft, RedondoBeach, 'Calih, assignor to North American Aviation, inc. Filed lluly 2, 1962, Ser. No. 206,352 @lalrns. (Cl. 313-314) This invention relates to a phase locking control device andmore particularly to such a device utilizing digital techniques in conjunction with a shift the desired control.

The phase locking of a device to a signal source is often required to assure precise control of the device in accordance with the signal source output. The phase locked device may be rotating machinery such as a motor or may be an electronic circuit such as a signal detector. The same basic servo techniques can be used in most instances regardless of the nature of the device to be controlled.

In achieving precise phase lock in the devices of the prior art, generally two separate modes of operation are utilized. The first of these brings the controlled device up to the frequency of the reference signal source. In the second mode of operation, different control circuitry is switched into the servo loop to achieve the desired phase lock condition. This type of dual mode operation has at least two disadvantages. Firstly, it requires separate circuitry for each mode of operation. Secondly, it presents problems in obtaining proper continuous control in view of the fact that it is difficult to determine the proper time to switch from the frequency control mode to the phase lock control mode with improper operation resulting should the switching be accomplished at the wrong time.

.The deviceof this invention overcomes the shortcomings of the prior art devices by providing a single mode of operation in achieving both frequency control and phase lock with a pulse signal source. This end result is attained by utilizing ashift register which is connected to receive the output of the pulse signal source and a signal indicating the output of the controlled device. The pulse signal source output is connected to drive the shift register in one direction while the output from the controlled device is connected to drive the shift register in an opposite direction.

The output of the shift register is either a speed up control signal in response to one predetermined set of register conditions or a slow down signal in response to 'a second set of predetermined register conditions. This speed up or slow down signal is fed to a control device which regulates the device to be controlled to achieve the desired locking condition. When there are more pulses arriving at the shift register input from the signal source'than from the controlled device, the shift register will be shifted so as to produce a speed up signal, while if there are more pulses arriving from the controlled device than from the pulse signal source, the shift register will be shifted to produce a slow down signal. When there are an equal number of pulses arriving from the signal source and the controlled device, the shift register will be shifted alternately to produce a speed up and a slowdown output. Such a signal as smoothed in. the control device will produce a control signal to maintain the controlled device at the desired frequency.

Phaselock of the controlled device with the signal source will beachieved when the pulses arriving at the register from the signal source and the controlled device are equispaced, i.e., when the pulses from the controlled device are arriving halfway between the time of arrival of successive pulses from the signal source. The control device will regulate the controlled device to achieve this desired end result in response to the output or" the shift register in achieving register without any switching from a frequency to a phase control mode. Phase lock is thus achieved with the output of the controlled device precisely lagging the signal source output by a predetermined amount.

The device of this invention thus achieves precise phase lock with a minimum of coinponents and a simple con tinuous type control. I i

It is therefore an object of this invention to provide an improved phase locking control device.

It is a further object of this invention to achieve phase lock of a controlled device to a pulse signal source without the requirement for switching between two modes of operation. 1

It is a further object of this invention to provide an improved phase locking device requiring less components and of simpler configuration than prior art devices.

It is still a further object of this invention to provide an improved phase locking control device utilizing a shift register.

Other objects of this invention will become apparent from the following description taken in conjunction with the accompanying drawings of which:

FIG. 1 is a block diagram illustrating the general features of the invention;

PEG. 2 is a block diagram illustrating an embodiment of the device of the invention as applied to the control-of a rnctorp PEG. 3 is a schematic diagram of a pulse resolver which may be utilized with the device of the invention;

FIGS. 4 and 5 are waveform drawings showing the waveforms at various points of the circuit illustrated in EH13;

And, PEG. 6 is a schematic diagram of a shift register which may be utilized in the device of the invention.

Referring now to FIG. 1, a block diagram illustrating basic operation of the device of t.e invention is shown. A pulse output signal is fed from pulse signal'source 12 to shift register 14. A pulse output signal is also fed from controlled device in indicative of the output thereof. The output of pulse signal source 12 is connected to shift register 14 so as to produce a shiftof this register towards the 1 position. The output of controlled device lb? is connected to shift register 14 so as to tend to shift the register towards the 4 position. Shift register 14 has a pair of or gates 17 and lawhich operate in conjunction therewith. When the digit is in shift register position 1 or 2, a first output signal is fed through or gate 17. On the other hand, when the digit is in shift register position 3 or 4, a second output signal is fed through or gate 1 5. Both of these signals are fed to control device 15.

The output signal fed through or gate 17 is a speed up signal whichis of a first predetermined nature while the signal fed through or gate His a slow down sig nal which is of a second predetermined nature Control device when receiving a'speed up signal will produce a control signal for controlled device 16so as to speed up or increase the frequency or advance the phase of -its output, while the opposite type of control is produced when a slow down signalis fed to control-device 15;; Such'speed up or slow down control is, of course, reflected in the output of controlled device 16 which is fed to shift register 14. Thus, when the shift register has been shifted to the l or 2 position which is indicative of the arrival of a greater number of pulses from pulse signal source 12 than from controlled device 16, a speed up signal will be fed through or. gate 17 from the shift register 14 to the control device15 which will'tendto increase the frequency of, the output of controlled'device 16. If there are more pulses arriving from the controlled device 16 than fromthe-pulse signal source 12, the shift register will be driven to the 3 or 4 position which will result in a slow down signal being fed through or gate 18 to control device 15 which will tend to decrease the frequency of the output of controlled device 16.

In starting the device from rest, the following occurs: Initially there are no pulses being fed from controlled device 16 to the shift register and only pulses from pulse signal source 12 are being fed thereto. The pulses from pulse signal source 12 will therefore shift the shift register all the way to position 1. It is to'be noted that the shift register, once it has been shifted to position 1 or 4,

will stay in these extreme positions until a shift pulse arrives to shift towards the opposite direction. When the shift register is in position 1, therefore, additional pulses from pulse signal source 12 will have no effect other than to keep the shift register in this position. As controlled device 16 speeds up, pulses will be fed therefrom to the shift register. As the correct speed is approached, the shift register will start shifting between positions 1 and 2. With the register in position 1 or 2 the controlled device will continue to accelerate until it is producing an output slightly higher in frequency than the signal source output. There will then be one more pulse coming from control device 16 than from the signal source .and this will cause a shift to the number 3 position which will produce a slow down signal. The shift register will then start to be shifted between positions 2 and 3 with signals arriving alternately from the pulse signal source and the controlled device.

The output of the controlled device will then be at the same frequency as that of the pulse signal source. However, the desired phase lock will not be achieved until the shift register is in the 2 and 3 positions for equal time intervals. This condition will only be achieved when the signals from the signal source and from the controlled device are equispaced with the signals from the controlled device arriving halfway in-between successive signals from the signal source. This phase locking operation will be automatically achieved by appropriate speed up or slow down control of controlled device 16. So, for example, if the pulses from controlled device 16* should be arriving too soon after the pulses from signal source 12, shift register 14 will be feeding a slow down"- signal for a longer time interval than a speed up signal, the net effect of which will be to slow down the output of controlled device 16. This Will tend to make the output pulses from controlled device 16 arrive a longer time interval after the arrival of the output of, signal source 12. When the speed up and slow down signals are being fed to the control device for equal time intervals, which condition will only incur when the input pulses from the shift register are equispaced, the desired phase locking condition will have been achieved.

Referring now to FIG. 2, a block diagram illustrating the device of the invention as incorporated into a motor control system is shown. The embodiment illustrated in FIG. 2 operates similarly to that of FIG. 1 except for the addition of pulse resolver 19 and the specific elements peculiar to the control of the rotation speed of a motor.

In the embodiment of FIG. 2, pulse resolver 19 is added between pulse signal source 12 and shift register 14 to take care of the situation where pulses from pulse signal source 12 and rotation sensor 23 should arrive spaced so'closely together so that the shift register is incapable "of detecting the second pulse to arrive in view of its inability to recover soon enough after the arrival of the first pulse. The particular shift register used may, for example, only have a resolution capability of 20 microseconds and may not be able to detect pulses arriving closer than that. This would mean that if a shift left pulse and a shift right pulse were to be fed to the shift register the 20 microsecond period the register would only respond to the first pulse arriving and would be incapable of responding to the second pulse. There,

therefore, would be an erronous shift in response to the In the device illustrated in FIG. 2, the current output from motor power source 20 is controlled by control device 15 to regulate the speed of motor 211. The current passed through control device 15 from power source 20 is regulated in accordance with the signal fed from shift register 14 through or gates 17 and 18. Rotation sensor 23 which may be an electrical pickoif or may involve an electrical switching device mechanically linked to motor 21 produces an output pulse with each rotation of motor 21. This output pulse is fed to pulse resolver l9. Pulse resolver 19 has twooutputs, one a series of shift left pulses which will tend to shift register 14 towards the 1 position and shift right pulses which tend to shift register it towards the 4 position. As already explained in connection with FIG. 1, the shift register output is either a speed up or slow down signal depending upon the shift condition of its digits.

Referring now to FIG. 3, a pulse resolver which may be utilized in the device of the invention is illustrated. Signals from pulse signal source 12 are fed in at terminal Tall while signals from rotation sensor 23 are fed inat terminal 31. The pulses arriving at terminal 30 are fed todrive blocking oscillator stage 34 into conduction. As is well known in the art, a blocking oscillator is normally biased to cutoff and when keyed to conduction will conduct through one cycle at its resonant frequency and then will return to a cutoff condition. The blocking oscillator produces as an output signal a pulse having a time duration which is a function of its circuit design characteristics. The time duration of the output pulses of blocking oscillater 34 is designed to be greamr than the minimum resolution capability of the shift register.

The pulses fed to terminal 31 from rotation sensor 23 are fed to drive blocking oscillator circuit 35 which is identical in characteristics to blocking oscillator circuit 34.

FIG. 4 illustrates the pulses generated by blocking oscillator circuits 34 and 35 in the situation where there is no overlap between the pulses, i.e., the two blocking oscillators are not conducting simultaneously. This is the situation where the input pulses are arriving at a time separation greater than the pulse widths of the blocking oscillator outputs which as noted are designed to be greater than the minimum resolution. capability of the shift register. The pulse developed in blocking oscillator circuit 34 is illustrated in line A of FIG. 4 while the pulse developed by blocking oscillator 35 is illustrated in line B of this same figure.

The output of blocking oscillator circiut 34 is fed through delay line 40 so that the differentiated positive going trailing edge thereof drives blocking oscillator oircuit 39 into conduction. Delay line 40 is designed to delay the firing of blocking oscillator circuit 39 for a period at least equal to the pulse duration of the output pulse from blocking oscillator circuit 34 which as already noted is predicated on the resolution capability of the shift register. As shown in line D of FIG. 4 which illustrates the trigger pulse fed to blocking oscillator circuit 39, the firing of this blocking oscillator is delayed after the trailing edge of the pulse output of oscillator 34 for the time interval T T Blocking oscillator circuit 43 operates similarly in response to the output of blocking oscillator circuit 35.

Blocki lg oscillator circuit 43 (FIG. 3) has its base input drive winding 46 connected through diode 50' to blocking oscillator winding 52 which is grounded. This same input Winding of blocking oscillator i2 is also. con nected through diode S to Winding 55 of blocking oscillaltor circuit 35. The common connection between diodes d, 54 and the input drive circuit for blocking oscillator 42 is connected through resistor do to terminal 63 to which a positive voltage source (not shown) is connected. When either blocking oscillator circuit 34 or 35 is in the cutoff condition, the input circuit of blocking oscillator 42 is effectively grounded through either diode 5d and inding 52 or diode 5d (and Winding 55. Therefore with no overlap in the conduction of blocking oscillator circuits 3d and 35, the input circuitry to blocking oscillator 4-2 will be maintained at ground potential, and this blocking oscillator will therefore be kept biased to, cutoff. Therefore, as indicated in line C of FIG. 4, there will be no output signal from this blocking oscillator Where th re is no overlap in the conduction of blocking oscillators and 35.

FIG. 5 illustrates what happens When there is any overlap between the conduction of blocking oscillators 3d and As can be seen, during the interval when such overlap is occurring, he pulse shown on line A will back bias diode db while the pulse shown on line B Will simultaneously back bias diode 54. This will remove the ground path from the input circuit of blocking oscillator 42. The positive potential fed from terminal 625 will therefore fire blocking oscillator 4-2 to produce a negative output signal as indicated on line C. The output signal from blocking oscillator 42 as indicated on line C is fed through diodes es and 67 to delay lines lli and ll respectively. These signals are delayed by the delay lines but produce-a cutoff signal as shown in line D at the inputs to blocking oscillators 39 and d3 preventing them from ever firing in response to the input pulses fed to terminals 3d and 3-1. ln this manner, output pulses are prevented from ever appearing at terminals 7t) and '71 when input pulses arrive at terminals 3% and 31 in less than a predetermined time interval.

Referring now to FIG. 6, a shift register which may A be utilized in the device of the invention is illustrated. Left shift pulses are fed from terminal 7d of the pulse resolver to terminal fill of the shift register While right shift pulses are fed from terminal Tl of the pulse resolver to terminal 81 of the shift register. The shift register comprises four shift units 35-38. These shift units are interconnected so that at all times one is cutoff while the other three are conducting. When the register is first turned on, one of these units, atrandom, will assume a non-conducting state. Let us assume, for example, that unit 87 is this non-conducting unit. it can be seen that with unit 87 non-conducting, the potential at the collector of this transistor will approach the positive potential at terminal 96. This positive potential appearing on the collector of transistor 87 will be coupled through diodes 92, 93, and 94 to the base circuits of transistors 86, 85, and 88 respectively to maintain these transistor units in a conducting state. Transistor 8'7 will be maintained on a cutoff condition by the negative potential fed to terminal res Wluch is connected to the base circuit of this transistor unit.

With transistor unit 87 at cutoff and transistor units 35, as, and 8S conducting, there will be a positive potential at the anode of diodes and MP3 and approximately zero potential at the anodes of diodes res, 1%7, lit-3, and 109. This can be verified by noting that diodes res, 107, M8, and lll'e are connected to the collector circuits of conducting transistors 85, 86, and 88 while the anodes of diodes ldil and 192 are both connected to the collector of the non-conducting transistor unit 87. The cathodes of diodes 102, 163, rss, 187, 1%, and M9 are all connected through appropriate biasing circuits to the positive potential established by zener diode 115.

Let us assume now that a left shift pulse should arrive at terminal This pulse is fed to the cathodes of dib odes M92, 1%,. and 109. Such an input pulse will not pass through diodes set or 199 in view of the fact that the anodes of these diodes are substantially at ground potential by virtue of their connections to the collectors of conducting transistors and the cathodes of these diodes have a positive potential on them sufficient tooverride the negative input shift pulse. This left shift pulse will, however, be passed through diode 192 in view of the fact that this diode has a positive potential on its anode by virtue of its connection to the collector ofa cutoff transistor, and this negative going shift pulse .appearing at the diodes cathode will therefore be sulficient to produce conduction thereof. This negative pulse is fed through capacitor ill) to the base circuit of transistor 86 driving it to cutoff. When transistor 86 is cutolfit will cause transistor 87 to conduct as Well as transistors 35 and 88 in the same fashion as described in connection with the operation of transistor unit 87. A left shift pulse on line 8t) will therefore produce a shift of one unit to the left, namely it will cause transistor unit 86 to assume the cutoff condition while maintaining the other units at conduction.

lf with the shift again in unit 87 (that is with this unit cutoff), a right shift pulse should arrive at terminal 81, this pulse will causetransistor unit 88 to go to cutoff with the other three units conducting in the same general fashion as explained in connection with the left shift. This occurs in View of the fact that the anode of diode N93 has a positive bias on it by virtue of its connection to the collector circuit of transistor 37 so that it will conduct on the arrival of a negative pulse at its cathode.

The shift units 33 are interconnected so that there can be a one unit shift to the left or the right With each input shifting pulse, the direction of such shift being determined by which line the input pulses are received on. With the shift in unit 88 (that is with this unit nonconducting), an additional right shift pulse at terminal 81 will have no effect in view of the fact that none of the other three transistors will have their input diodes biased so as to be made to conduct on the arrival of such a pulse. Similarly the arrival of a left shift pulse with the shift in unit 85 will have no effect. Thus, when the shift arrives at the end of the line in either direction, shifting can only be accomplished in the opposite direction. Zener diode isutilized to provide a predetermined fixed bias at the cathodes of diodes 1&2, 1&3, and 166- ltl? to assure proper response to the input signals. Zener diode 11.7 is utilized to generate a precise output signal. Zener diode 117 will be fired when the shift is in either unit S7 or 8-3, that is When either of these units is in the non-conducting-state. As can be seen, when-such is the case, a positive potential will appear between the cathode and the anode of Zener diode 11.7 as presented through diode 12d when transistor unit 87 is. non-conducting and diode 121 when transistor unit 83 is nonconducting. Thus a current flow will be produced through zener diode lit? and diode 22 to provide an output signal indidating that the shift is in units 537 or 88. When the shift is in units 85 or 86, zener diode Ill? is kept non-conducting and no output current signal is pro duced.

The output control signal is fed from terminal 127 to an appropriate regulator circuit which utilizes this signal to speed up the motor while zener diode 117 is conducting and to slow down the motor when it is nonconducting. An integrating circuit may be used in this regulator so that the average conduction of zener diode 117 is utilized to determine the speed of the motor. With zener diode conducting and non-conducting for equal intervals, an average regulator current output will be maintained to precisely phase lock the controlled device to the signal source. Appropriate amplified and regulator circuits capable of utilizing the output appearing at terminal 127 are Well known in the art and may include a device such as a pulse width modulator or a simple series amazes Z transistor regulator connected to control the current fed from the power source to the motor or other device to be controlled. 7

The device of this invention thus provides a simple yet highly effective device for phase looking a device to be controlled such as a motor to a pulse signal source. Frequency and phase lock are attained without the necessity of switching from one mode of Operation to another, thus providing continuous, precise control, and minimizing the circuitry required to achieve the desired end results.

Although the invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of this invention being limited only by the terms of the appended claims.

I claim:

1. A device for phase locking a device to be controlled with a pulse signal source output comprising,

a shift register connected to receive said pulse signal source output and a signal indicating the output of said device to be controlled,

said pulse signal source output being connected to drive said shift register in one direction,

said signal indicating the output of said device to be controlled connected to drive said shift register in a direction opposite said one direction, and

control means interposed between said shift register and said device to be controlled for regulating the input to said device to be controlled in response to said shift register output,

said control means having an output consisting solely of one or the other of two fixed magnitudes, one in response to a first plurality of predetermined shift register conditions and a second in response to a second plurality of predetermined shift register conditions.

2. The device as recited in claim 1 wherein said first plurality of predetermined shift register conditions results in a speed up signal being fed to said control means and said second plurality of predetermined shift register conditions results in a slow down signal being fed to said control means.

3. A device for phase looking a device to be controlled with a pulse signal source output comprising,

a shift register connected to receive a signal in accordance with said pulse signal source output and a signal indicating the output of said controlled device to be controlled,

said pulse signal source output being connected to drive said shift register in one direction,

said signal indicating the output of said device to be controlled being connnected to drive said shift register in a direction opposite said one direction,

control means interposed between said shift register and said device to be controlled for regulating the input to said device to be controlled in response to said shift register output,

said control means having an output consisting solely of one fixed magnitude in response to a first plurality of predetermined shift register conditions and an output consisting solely of a second fixed magnitude in response to a second plurality of predetermined shift register conditions, and

pulse resolver means interposed between said pulse signal source and said shift register and said device to be controlled and said shift register for passing signals to said shift register only when the signal from said pulse signal source and the output from said device to be controlled are separated by at least a predetermined minimum time interval, said pulse resolver means preventing pulses from either said pulse signal source or the output of said device from being passed when not separated by at least a predetermined minimum time.

4. The device as recited in claim 3 wherein said shift register has at least four positions.

said first set of predetermined register conditions being satisfied when said register is in one of a first half of said positions,

said second set of predetermined register conditions being satisfied when said register is in one of a second half of said positions.

5. A device for phase locking rotation of a motor to a reference source signal comprising,

means for sensing rotation of said motor,

pulse resolver means connected to receive the outputs of said sensing means and said reference source, said pulse resolver means preventing pulses of either said reference source signal or from said means for sensing, from passing when not separated by at least a predetermined minimum time,

a shift register connected to receive the output of said pulse resolver means,

said sensing means output being connected to drive said shift register in one direction,

said reference source output being connected to drive said shift register in a direction opposite said one direction,

a motor power source, and

speed regulator means responsively connected to said shift register interposed between said power source and said motorfor controlling the current fed to said motor to synchronize rotation thereof With said reference source signal, said speed regulator providmg an output consisting solely of one or the other of two fixed magnitudes, one of which causes said motor to increase speed and the other of which causes said motor to decrease speed.

References @ited by the Examiner UNITED STATES PATENTS 2,537,427 1/51 Seid et a1. 318-28 2,829,323 4/58 Steele 318-28 2,876,365 3/59 Slusser 307-885 2,932,778 4/60 Curtis 318-318 2,996,649 8/61 Leslie 318-314 3,005,917 10/61 Hofmann 307-885 3,048,711 8/62 Hofmann 307-885 3,064,173 11/62 Breen et a1. 318-314 3,070,713 12/62 Leightner 307-885 EOHN F. COUCH, Primary Examiner. 

1. A DEVICE FOR PHASE LOCKING A DEVICE TO BE CONTROLLED WITH A PULSE SIGNAL SOURCE OUTPUT COMPRISING, A SHIFT REGISTER CONNECTED TO RECEIVE SAID PULSE SIGNAL SOURCE OUTPUT AND A SIGNAL INDICATING THE OUTPUT OF SAID DEVICE TO BE CONTROLLED, SAID PULSE SIGNAL SOURCE OUTPUT BEING CONNECTED TO DRIVE SAID SHIFT REGISTER IN ONE DIRECTION, SAID SIGNAL INDICATING THE OUTPUT OF SAID DEVICE TO BE CONTROLLED CONNECTED TO DRIVE SAID SHIFT REGISTER IN A DIRECTION OPPOSITE SAID ONE DIRECTION, AND CONTROL MEANS INTERPOSED BETWEEN SAID SHIFT REGISTER AND SAID DEVICE TO BE CONTROLLED FOR REGULATING THE INPUT TO SAID DEVICE TO BE CONTROLLED IN RESPONSE TO SAID SHIFT REGISTER OUTPUT, SAID CONTROL MEANS HAVING AN OUTPUT CONSISTING SOLELY OF ONE OR THE OTHER OF TWO FIXED MAGNITUDES, ONE IN RESPONSE TO A FIRST PLURALITY OF PREDETERMINED SHIFT REGISTER CONDITIONS AND A SECOND IN RESPONSE TO A SECOND PLURALITY OF PREDETERMINED SHIFT REGISTER CONDITIONS. 